4096-bits serial electr ically erasable prom am93lc66 this datasheet contains new product information. anachip corp. reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev.a1 oct 20, 2003 1/10 atc features ? state-of-the-art architecture - non-volatile data storage - standard voltage and low voltage operation vcc: 2.7v ~ 5.5v - full ttl compatible inputs and outputs - auto increment read for efficient data dump ? hardware and software write protection - defaults to write-disabled state at power up - software instructions for write-enable/disable - vcc level verification before self-timed programming cycle ? advanced low voltage cmos eeprom technology ? versatile, easy-to-use interface - self-timed programming cycle - automatic erase-before-write - programming status indicator - word and chip erasable - stop sk anytime for power savings ? durability and reliability - 40 years data retention - minimum of 1m write cycles per word - unlimited read cycles - esd protection connection diagram 1 2 3 4 8 7 6 5 vcc gnd nc org cs sk pdip-8l / sop-8l do di 1 2 3 4 8 7 6 5 vcc gnd nc org cs sk rotated sop-8l do di general description the am93lc66 is the 4096-bit non-volatile serial eeprom. it is manufactured by using atc's advanced cmos eeprom technology. the am93lc66 provides efficient non-volatile read/write memory arranged as 256 words of 16 bits each when the org pin is connected to vcc and 512 words of 8 bits each when it is tied to ground. the instruction set includes read, write, and write enable/disable functions. the data out pin (do) indicates the status of the device during the self-timed non-volatile programming cycle. the self-timed write cycle includes an automatic erase-before-write capability. only wh en the chip is in the write enable state and proper vcc operation range is the write instruction accepted and thus to protect against inadvertent writes. data is written in 16 bits per write instruction into the selected register. if chip select (cs) is brought high after initiation of the write cycle, the data output (do) pin will in dicate the ready/busy status of the chip. the am93lc66 is available in space-saving 8-lead pdip, 8-lead sop and rotated 8-lead sop package. pin assignments name description cs chip select sk serial data clock di serial data input do serial data output gnd ground vcc power supply nc no connection org internal organization ordering information type package 66: 4k s : sop-8l gs : sop-8l,g type n : pdip-8l temp. grade am 93 l c 66 x xx x packing blank : c o 70 ~ c o 0 + i : c o 85 ~ c o 40 + ? v : c o 125 ~ c o 40 + ? blank : tube a : taping operating voltage lc : 2.7~5.5v,cmos
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 2/10 atc block diagrams instruction register (11 bits) instruction decode control and clock generation data register address register v cc range detector write enable dummy bit r/w amps decoder high voltage generator eeprom array (256 x 16) or (512 x 8) di cs sk do org absolute maximum ratings characteristics symbol values unit storage temperature t s -65 to + 125 c voltage with respect to ground -0.3 to + 6.5 v note: these are stress rating only. appropriate conditions for operating these devices given elsewhere may permanently damage the part. prolonged exposure to maximum ratings may affect device reliability. operating conditions temperature under bias values unit am93lc66 0 to + 70 c am93lc66i -40 to + 85 c am93lc66v -40 to +125 c dc electrical characteristics (vcc =2.7~5.5v, ta = 25 o c , unless otherwise noted) parameter symbol conditions min max units operating current** i cc cs=v ih , sk=1mhz cmos input levels 3 ma standby current i sb cs=di=sk=0v 10 a input leakage i il v in = 0v to v cc(cs,sk,di) -1 1 a output leakage i ol v out = 0v to v cc , cs=0v -1 1 a v cc = 3v + 10% -0.1 0.15 v cc input low voltage** v il v cc = 5v + 10% -0.1 0.8 v v cc = 3v + 10% 0.8 v cc v cc +0.2 input high voltage** v ih v cc = 5v + 10% 2 v cc +0.2 v output low voltage v ol1 i ol = 2.1ma ttl, v cc =5v + 10% 0.4 v output high voltage v oh1 i oh = -400ua ttl, v cc =5v + 10% 2.4 v output low voltage i ol = 10ua cmos 0.2 v output high voltage v ol2 i oh = -10ua cmos v cc -0.2 v note **: i cc , v il min and v ih max are for reference only and are not tested
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 3/10 atc ac electrical characteristics (vcc = 2.7v ~ 5.5v, ta = 25 o c , unless otherwise noted) am93lc66 parameter symbol conditions min max units sk clock frequency f sk 0 1 mhz sk high time t skh 250 ns sk low time t skl 250 ns minimum cs low time t cs 250 ns cs setup time t css relative to sk 50 ns di setup time t dis relative to sk 100 ns cs hold time t csh relative to sk 0 ns di hold time t dih relative to sk 100 ns output delay to "1" t pd1 ac test 500 ns output delay to "0" t pd0 ac test 500 ns cs to status valid t sv ac test cl = 100pf 500 ns cs to do in 3-state t df cs = vil 100 ns write cycle time t wp 10 ms 5v, 25oc, page mode endurance** 1m write cycles note** : the parameter is characterized and isn?t 100% tested. figure 1. ac test conditions 632 ohm do 1.247v (1 ttl gate load) 100pf instruction set address input data instruction start bit op code 8 16 8 16 read 1 10 a 8 - a 0 a 7 - a 0 wen (write enable) 1 00 11 xxxxxxx 11xxxxxx write 1 01 a 8 - a 0 a 7 - a 0 d 7 ? d 0 d 15 - d 0 wrall (write all registers) 1 00 01xxxxxxx 01xxxxxx d 7 ? d 0 d 15 - d 0 wds (write disable) 1 00 00 xxxxxxx 00xxxxxx erase 1 11 a 8 - a 0 a 7 - a 0 eral (erase all registers) 1 00 10 xxxxxxx 10xxxxxx
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 4/10 atc pin capacitance ** (ta=25 c , f=1mh z ) symbol parameter max units c out output capacitance 5 pf c in input capacitance 5 pf note ** : the parameter is characterized and isn?t 100% tested. functional descriptions applications the am93lc66 is ideal for high volume applications requiring low power and low density storage. this device uses a low cost, space saving 8-pin package. typical applications include robotics, alarm devices, electronic locks, meters and instrumentation settings such as lan cards, monitors and modem. endurance and data retention the am93lc66 is designed for applications requiring up to 1m programming cycles (write, wrall, earse and erall) . it provides 40 years of secure data retention. device operation the am93lc66 is controlled by seven 11-bit instructions. instructions are clocked in (serially) on the di pin. each instruction begins with a logical "1" (the start bit). this is followed by the opcode (2 bits), the address field (8 bits), and data, if appropriate. the clock signal (sk) may be halted at any time and the am93lc66 will remain in its last state. this allows full static flexib ility and maximum power conservation. read (read) the read instruction is th e only instruction that outputs serial data on the do pin. after the read instruction and address have been decoded, data is transferred from the selected memory register into a 8-bit or 16-bit serial shift register. (please note that one logical "0" bit precedes the actual 8-bit or 16-bit output data string.) the output on do changes during the rising edge transitions of sk. (shown in figure 3) auto increment read operations sequential read is possible, since the am93lc66 has been designed to output a continuous stream of memory content in response to a single read operation instruction. to utilize this function, the system asserts a read instruction specifying a start location address. once the 8-bit or 16-bit of the addressed word have been clocked out, the data in consecutively higher address locations is output. the address will wrap around continuously with cs high until the chip select (cs) control pin is brought low. this allows for single instruction data dumps to be executed with a minimum of firmware overhead. write enable (wen) before any device programming (write, wrall, erase, and eral) can be done, the write enable (wen) instruction must be executed first. when vcc is applied, this device powers up in the write disable state. the device then remains in a write disable state unt il a wen instruction is executed. thereafter the device remains enabled until a wds instruct ion is executed or until vcc is removed. (note: neither the wen nor the wds instruction has any effect on the read instruction.) (shown in figure 4) write disable (wds) the write disable (wds) instruction disables all programming capabilities. th is protects the entire part against accidental modification of data until a wen instruction is executed. (when vcc is applied, this part powers up in the write disable state.) to protect data, a wds instruction should be executed upon completion of each programming operation. (note: neither the wen nor the wds instruction has any effect on the read instruction.) (shown in figure 5)
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 5/10 atc functional descriptions (continued) write (write) the write instruction includes 8-bit or 16-bit of data to be written into the specified register. after the last data bit has been applied to di, and before the next rising edge of sk, cs must be brought low. the falling edge of cs initiates the self-timed programming cycle. after a minimum wait of 250ns (5v operation) from the falling edge of cs (tcs), do will indicate the ready/busy status of the chip if cs is brought high. this means that logical "0" implies the programming is still in progress while logical "1" indicates the selected register has been written, and the part is ready for another instruction. (see figure 6) note : the combination of cs high, di high and the rising edge of the sk clock, resets the ready/busy flag. therefore, it is important if you want to access the ready/busy flag, not to reset it through this combination of control signals. before a write instruction can be executed, the device must be in the write enable (wen) state. write all (wrall) the write all (wrall) in struction programs all registers with the data pattern specified in the instruction. while the wr all instruction is being loaded, the address field becomes a sequence of don't-care bits. (shown in figure 7) as with the write instruction, if cs is brought high after a minimum wait of 250ns (tcs), the do pin indicates the ready/busy status of the chip. (shown in figure 7) erase (erase) after the erase instruction is entered, cs must be brought low. the falling edge of cs initiates the self-timed internal programming cycle. bringing cs high after minimum of tcs, will cause do to indicate the read/busy status of the chip. to explain this, a logical "0" indicates the programming is still in progress while a logical "1" indicates the erase cycle is complete and the part is ready for another instruction. (show n in figure 8) erase all (erall) full chip erase is provided for ease of programming. erasing the entire chip involv es setting all bits in the entire memory array to a logical "1". (shown in figure 9) security consideration to protect the entire part against accidental modification of data, each programming instruction (write, wrall, erase, and erall) must satisfy two conditions before us er initiate self-timed programming cycle (the fallin g edge of cs). one is that the am93lc66 is at wen status. the other is that the vcc value must exceed a lock-out value which can be adjusted by analog technology inc.
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 6/10 atc timing diagram (1) figure 2. synchronous data timing t t skh t skl t csh t css cs sk di do(read) do(write) (wrall) (erase) (erall) t sv status valid t df t df t pd1 t pdo t dis t dih figure 3. data read cycle timing cs sk + ao an 0 1 1 di dn do o do tri-state +for all instructions, sk cycles before start bit don't care. *address pointer cycle to the next register. * t cs
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 7/10 atc timing diagram (2) do = tri-state **a n-2 ~a0 don't care. figure 4. write enable(wen) cycle timing t cs cs sk di 1 1 0 0 1 x- - - - - - - - - - - x ** figure 5. write disable(wds) cycle timing do = tri-state **a n-2 ~a0 don't care. cs t cs sk di 10 0 00 x- - - - -- - - - x ** figure 6. write(write) cycle timing t cs cs do tri-state t sv t df busy ready t wp sk di 1 0 1 a n ao d n do
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 8/10 atc timing diagrams (3) t cs cs sk busy ready do tri-state t sv t wp **a n-2 ~a0 don't care. figure 7. write all(wrall) cycle timing di 1 00 0 1 dn do x- - - - - - - - - - - -x ** figure 8. erase(erase) cycle timing sk di do tri-state 111 an ao t sv busy ready t wp t df t cs cs figure 9. erase all(erall) cycle timing t cs cs sk do tri-state t sv t df t wp busy ready **a n-2 ~a0 don't care. di 100 1 x- - - - - - - - - x 0 **
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 9/10 atc package diagrams (1) plastic dual-in-line package: pdip-8l e1 d 7 (4x) a l a2 a1 b2 b1 b e s 15 (4x) e c eb e-pin o0.118 inch pin #1 indent o0.025 deep 0.006-0.008 inch dimensions in millimeters dimensions in inches symbol min. nom. max. min. nom. max. a - - 5.33 - - 0.210 a1 0.38 - - 0.015 - - a2 3.1 3.30 3.5 0.122 0.130 0.138 b 0.36 0.46 0.56 0.014 0.018 0.022 b1 1.4 1.52 1.65 0.055 0.060 0.065 b2 0.81 0.99 1.14 0.032 0.039 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 d 9.02 9.27 9.53 0.355 0.365 0.375 e 7.62 7.94 8.26 0.300 0.313 0.325 e1 6.15 6.35 6.55 0.242 0.250 0.258 e - 2.54 - - 0.100 - l 2.92 3.3 3.81 0.115 0.130 0.150 eb 8.38 8.89 9.40 0.330 0.350 0.370 s 0.71 0.84 0.97 0.028 0.033 0.038
4096-bits serial electr ically erasable prom am93lc66 anachip corp. www.anachip.com.tw rev. a1 oct 20, 2003 10/10 atc (2) jedec small outline package: sop-8l view "a" l h e c view "a" a a2 a1 b e d 7 (4x) 0.015x45 7 (4x) y dimensions in millimeters dimensions in inches symbol min. nom. max. min. nom. max. a 1.40 1.60 1.75 0.055 0.063 0.069 a1 0.10 - 0.25 0.040 - 0.100 a2 1.30 1.45 1.50 0.051 0.057 0.059 b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.19 0.20 0.25 0.0075 0.008 0.010 d 4.80 5.05 5.30 0.189 0.199 0.209 e 3.70 3.90 4.10 0.146 0.154 0.161 e - 1.27 - - 0.050 - h 5.79 5.99 6.20 0.228 0.236 0.244 l 0.38 0.71 1.27 0.015 0.028 0.050 y - - 0.10 - - 0.004 0 o - 8 o 0 o - 8 o marking information top view part number (x:id code) blank : pdip-8l & sop-8l (commercial) i : pdip-8l & sop-8l (industrial) v : pdip-8l & sop-8l (automotive) g : rotated sop-8l (commercial) b : rotated sop-8l (industrial) d : rotated sop-8l (automotive) atc 93lc66x yy w w x logo date & id code yy : year ww : week x: internal
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